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TDA7348
Digitally controlled audio processor
Features
Input multiplexer - - Three stereo and one mono inputs Selectable input gain for optimal adaptation to different sources

Volume control in 0.3db steps including gain up to 20dB Zero crossing mute and direct mute Pause detector with programmable threshold Soft mute controlled by software or hardware PIN Bass and treble control Four speaker attenuators - Four independent speakers control in 1.25dB steps for balance and fader facilities Independent mute function
SO-28
-
All functions programmable via serial I2C bus
instead of standard bipolar multipliers, very low distortion and very low noise are obtained Several new features like softmute, zero-crossing mute and pause detector are implemented. The Soft Mute function can be activated in two ways, either via the serial bus (bit D0, Mute Byte), or directly on pin 22 through an I/O line of the microcontroller Very low DC stepping is obtained by use of a BICMOS technology.
Description
The TDA7348 is an upgrade of the TDA7318 audioprocessor. Thanks to the used BIPOLAR/CMOS technology, very low distortion, low noise and DC-stepping are obtained. Due to a highly linear signal processing, using CMOS-switching techniques
Order codes
Part number TDA7348D TDA7348D013TR E-TDA7348D
(1) (1)
Package SO-28 SO-28 SO-28 SO-28
Packing Tube Tape and reel Tube Tape and reel
E-TDA7348D013TR
1. This device is Pb-free Ecopack , see Chapter 5 Package information.
January 2007
Rev 3
1/20
www.st.com 1
Contents
TDA7348
Contents
1 2 3 Block diagram and PIN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 I2C BUS interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 3.2 3.3 3.4 3.5 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Transmission without acknowledgement . . . . . . . . . . . . . . . . . . . . . . . . . 10
4
Software specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 4.2 4.3 4.4 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Auto increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Transmitted data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Data byte specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 6
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/20
TDA7348
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Subaddress (receive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Send mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Input Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Loudness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Speaker attenuators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bass/Treble. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3/20
List of figures
TDA7348
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PIN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Data validity on the I2C BUS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Timing diagram of I2C BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Acknowledge on the I2C BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SO-28 mechanical, data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4/20
TDA7348
Block diagram and PIN connections
1
Figure 1.
Block diagram and PIN connections
Block diagram
C10 2.2F R2 4.7K C14 100nF SM BOUT(L) 22 19 C15 100nF 4 C16 2.7nF TREBLE(L) SPKR ATT 26 MUTE ZERO CROSS + MUTE VOL 1, 2 BASS TREBLE OUT LEFT FRONT
OUT(L) 17
IN(L) 16
BIN(L) 18
3x 1F C1 LEFT INPUTS C2 C3
RB L1 L2 L3 14 13 12 L1 L2 L3 L4
SPKR ATT 24 MUTE OUT LEFT REAR
C4
11
INPUT SELECTOR + GAIN
28 SOFT MUTE SERIAL BUS DECODER + LATCHES 27
SCL SDA
BUS
3x 1F C7 RIGHT INPUTS C6 C5
R4 R3 R2 R1 8 9 10 R3 R2 R1 ZERO CROSS + MUTE VOL 1, 2 BASS TREBLE
SPKR ATT 25 MUTE OUT RIGHT FRONT
SPKR ATT RB 23 MUTE 1 7 OUT(R) 10F C9 2.2F 6 IN(R) CSM 47nF 15 CSM C11 100nF R1 4.7K 21 20 BOUT(R) 5 BIN(R) C12 100nF TREBLE(R)
D93AU100B
VS
2
SUPPLY 3
OUT RIGHT REAR
AGND
CREF C8
C13 2.7nF
Figure 2.
PIN connections
CREF VS GND TREBLE L R IN(R) OUT(R) IN R3 IN R2 IN R1 AM MONO IN L3 IN L2 IN L1
1 2 3 4 5 6 7 8 9 10 11 12 13 14
D94AU099
28 27 26 25 24 23 22 21 20 19 18 17 16 15
SCL SDA OUT LF OUT RF OUT LR OUT RR SM BOUT(R) BIN(R) BOUT(L) BIN(L) OUT(L) IN(L) CSM
BUS INPUTS
BASS
5/20
Electrical characteristics
TDA7348
2
Electrical characteristics
Table 1. Electrical characteristics VS = 9V; RL = 10K; Rg = 50; Tamb = 25C; all controls flat (G = 0.3dB step 0dB); f = 1KHz. Refer to the test circuit, unless otherwise specified.
Parameter Test Condition Min. Typ. Max. Unit
Symbol Input selector RI VCL SI RL GI MIN GI MAX Gstep eN VDC
Input resistance Clipping level Input separation Output load resistance Minimum input gain Maximum input gain Step resolution Input noise DC steps GIMIN to GIMAX 20Hz to 20 KHz unweighted Adiacent gain steps d 0.3%
70 2.1 80 2 -0.75
100 2.6 100
130
K VRMS dB K
0
0.75
dB dB dB V
10.25 11.25 12.25 2.75 3.75 2.3 1.5 3 10 4.75
mV mV
Volume control (1 + 2) RI GMAX AMAX ASTEPC ASTEPF EA Et VDC Input resistance Maximum gain Maximum attenuation Step resolution coarse attenuation Step resolution fine attenuation G = 20 to -20dB Attenuation set error G = -20 to -58dB Tracking error Adiacent attenuation steps DC steps From 0dB to AMAX 0.5 5 mV -3 0 -3 2 2 3 dB dB mV 0.5 0.11 -1.25 35 18.75 50 20 78.45 1.25 0.31 0 2.0 0.51 1.25 21.25 K dB dB dB dB dB
Zero crossing mute WIN = 11 VTH Zero crossing threshold WIN = 10 WIN = 01 WIN = 00 AMUTE VDC Mute attenuation DC step 0dB to Mute 80 20 40 80 160 100 0 3 mV mV mV mV dB mV
6/20
TDA7348 Table 1.
Electrical characteristics Electrical characteristics (continued) VS = 9V; RL = 10K; Rg = 50; Tamb = 25C; all controls flat (G = 0.3dB step 0dB); f = 1KHz. Refer to the test circuit, unless otherwise specified.
Parameter Test Condition Min. Typ. Max. Unit
Symbol Soft mute AMUTE TDON
Mute attenuation ON delay time CCSM = 22nF; 0 to -20dB; I = IMAX CCSM = 22nF; 0 to -20dB; I = IMIN
45 0.7 20 25
60 1 35 50 1 1.7 55 75
dB ms ms A A 3.5 65 V K V 1 V
TDOFF VTHSM RINT VSMH VSML
OFF delay time Soft mute threshold Pull-up resistor (pin 22) (pin 22) level high (pin 22) level low
VCSM = 0V; I = IMAX VCSM = 0V; I = IMIN
1.5 35 Soft Mute active 3.5
2.5 50
Bass control BBOOST BCUT Astep Rg Max bass boost Max bass cut Step resolution Internal feedback resistance 15 -8.5 1 45 18 -10 2 65 20 -11.5 3 85 dB dB dB K
Treble control CRANGE Astep Control range Step resolution 13 1 14 2 15 3 dB dB
Speaker attenuators CRANGE
Astep
Control range Step resolution Output mute attenuation Attenuation set error DC steps Adjacent attenuation steps Data word = XXX11111
35 0.5 80
37.5 1.25 100
40 2.0
dB dB dB
AMUTE EA VDC
1.25 0 3
dB mV
Audio output Vclip RL RO VDC General VCC Supply voltage 6 9 10.2 V Clipping level Output load resistance Output impedance DC voltage level 3.5 d = 0.3% 2.1 2 30 3.8 100 4.1 2.6 Vrms K W V
7/20
Electrical characteristics Table 1.
TDA7348
Electrical characteristics (continued) VS = 9V; RL = 10K; Rg = 50; Tamb = 25C; all controls flat (G = 0.3dB step 0dB); f = 1KHz. Refer to the test circuit, unless otherwise specified.
Parameter Supply current f = 1KHz Power supply rejection ratio B = 20 to 20kHz "A" weighted Output Muted (B = 20 to 20kHz flat) 65 2.5 5 0 0 106 80 Vin = 1V 100 0.01 0.08 15 1 2 dB V V dB dB dB dB % Test Condition Min. 5 60 Typ. 10 80 Max. 15 Unit mA dB
Symbol ICC PSRR
eNO
Output noise All Gains 0dB (B = 20 to 20kHz flat)
Et S/N SC d
Total tracking error Signal to noise ratio Channel separation Distortion
AV= 0 to -20dB AV= -20 to -60dB All Gains = 0dB; VO= 1Vrms
Bus inputs VIL VlN IlN VO Input low voltage Input high voltage Input current Output voltage SDA acknowledge VIN = 0.4V IO = 1.6mA 3 -5 0.4 5 0.8 1 V V A V
Table 2.
Symbol VS Tamb Tstg
Absolute maximum ratings
Parameter Operating supply voltage Operating ambient temperature Storage temperature range Value 10.5 -40 to 85 -55 to 150 Unit V C C
Table 3.
Symbol
Thermal data
Parameter SO28 65 Unit C/W
Rth j-amb Thermal Resistance Junction pins
Table 4.
Symbol
VS VCL
Quick reference data
Parameter Supply voltage Max. input signal handling Total harmonic distortion V = 1Vrms f = 1KHz Signal to noise ratio Min. 6 2.1 Typ. 9 2.6 0.01 106 0.08 Max. 10.2 Unit V Vrms % dB
THD S/N
8/20
TDA7348 Table 4.
Symbol
SC
Electrical characteristics Quick reference data (continued)
Parameter Channel separation f = 1KHz Volume control Treble control 2dB step Bass control 2dB step Fader and balance control 1.25dB step Input gain 3.75dB step Mute attenuation 78.45 -14 -10 38.75 0 100 Min. Typ. 100 20 +14 +18 0 11.2 5 Max. Unit dB dB dB dB dB dB dB
9/20
I2C BUS interface
TDA7348
3
I2C BUS interface
Data transmission from microprocessor to the TDA7348 and vice-versa takes place through the 2 wires of the I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to the positive supply voltage must be externally connected).
3.1
Data validity
As shown in Figure 3., the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
3.2
Start and stop conditions
As shown in Figure 4. a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP conditions must be sent before each START condition.
3.3
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first.
3.4
Acknowledge
The master (microprocessor) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see Figure 5.). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer.
3.5
Transmission without acknowledgement
The microprocessor can use a simpler transmission, if it avoids detection of the acknowledgement from the audio processor. It simply waits one clock pulse without checking the slave acknowledgment, and sends the new data. This approach of course is less protected from errors, increases the possibility of interference, and decreases the immunity to noise.
10/20
TDA7348 Figure 3. Data validity on the I2C BUS
I2C BUS interface
SDA
SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED
D99AU1031
Figure 4.
Timing diagram of I2C BUS
SCL I2CBUS SDA
D99AU1032
START
STOP
Figure 5.
Acknowledge on the I2C BUS
SCL
1
2
3
7
8
9
SDA MSB START
D99AU1033
ACKNOWLEDGMENT FROM RECEIVER
11/20
Software specification
TDA7348
4
4.1
Software specification
Interface protocol
The interface protocol comprises:

A start condition (s) A chip address byte, (the LSB bit determines read/write transmission) A subaddress byte. A sequence of data (N-bytes + acknowledge) A stop condition (P)
Subaddress Data 1 to data n
Chip address
MSB S 1
LSB 0 0 0 1 0 0 R/W ACK
ACK = Acknowledge S = Start P = Stop I = Auto Increment X = Not used Max clock speed 500kbits/s
MSB X XX
LSB I A3 A2 A1 A0 ACK
MSB DATA
LSB ACK P
4.2
Auto increment
If bit I in the subaddress byte is set to "1", the auto-increment of the subaddress is enabled Table 5.
MSB X X X I A3 0 0 0 0 0 0 0 0 1 A2 0 0 0 0 1 1 1 1 0 A1 0 0 1 1 0 0 1 1 0
Subaddress (receive mode)
LSB A0 0 1 0 1 0 1 0 1 0 Input selector Loudness Volume Bass, Treble Speaker attenuator LF Speaker attenuator LR Speaker attenuator RF Speaker attenuator RR Mute Function
12/20
TDA7348
Software specification
4.3
Transmitted data
Table 6.
MSB X X X X X SM ZM
Send mode
LSB X
ZM = Zero crossing muted (HIGH active) SM = Soft mute activated (HIGH active) X = Not used The transmitted data is automatically updated after each ACK. Transmission can be repeated without new chip address.
4.4
Data byte specification
X = not relevant; set to "1" during testing Table 7.
MSB D7 X X X X X X X X X X X X D6 X X X X X X X X X X X X D5 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 D4 D3 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1
Input Selector
LSB Function D0 0 1 0 1 0 1 0 1 not used IN 2 IN 1 AM mono not used IN 3 not allowed not allowed 11.25dB gain 7.5dB gain 3.75dB gain 0dB gain
For example to select the IN 2 input with a gain of 7.5dB the Data Byte is: X X 1 0 1 0 0 1
Table 8.
MSB D7 X X X
Loudness
LSB Function D6 X X X D5 X X X D4 1 1 1 D3 0 0 0 D2 0 0 0 D1 0 0 1 D0 0 1 0 0dB -1.25dB -2.5dB
13/20
Software specification Table 8.
MSB D7 X X X X X X X X X X X X X D6 X X X X X X X X X X X X X D5 X X X X X X X X X X X X X D4 1 1 1 1 1 1 1 1 1 1 1 1 1 D3 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 1 0 0 1 1 0 0 1 1 0 0 1 1
TDA7348 Loudness (continued)
LSB Function D0 1 0 1 0 1 0 1 0 1 0 1 0 1 -3.75dB -5dB -6.25dB -7.5dB -8.75dB -10dB -11.25dB -12.5dB -13.75dB -15dB -16.25dB -17.5dB -18.75dB
For example to select -17.5dB attenuation, loudness OFF, the Data Byte is: X X X1 1 1 1 0
Table 9.
MSB D7 D6
Mute
LSB Function D5 D4 D3 D2 D1 D0 1 0 1 1 0 0 1 0 0 1 1 0 1 0 1 1 0 1 1 Soft mute on Soft mute with fast slope (I = IMAX) Soft mute with slow slope (I = IMIN) Direct mute Zero crossing mute on Zero crossing mute off (delayed until next zerocrossing) Zero crossing mute and pause detector reset 160mV ZC window threshold (WIN = 00) 80mV ZC window threshold (WIN = 01) 40mV ZC window threshold (WIN = 10) 20mV ZC window threshold (WIN = 11) Non-symmetrical Bass Cut Symmetrical Bass Cut
0 1
14/20
TDA7348
Software specification An additional direct mute function is included in the speaker attenuators.
Note:
Bass cut for very low frequencies should not be used at +16 & +18dB bass boost (DC gain) Table 10.
MSB D7 D6 D5 D4 D3 D2 D1
Speaker attenuators
LSB Speaker attenuator LF, LR, RF, RR D0 1.25dB step
X X X X X X X X
X X X X X X X X
X X X X X X X X
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0dB -1.25dB -2.5dB -3.75dB -5dB -6.25dB -7.5dB -8.75dB 10dB step
X X X X X
X X X X X
X X X X X
0 0 1 1 1
0 1 0 1 1 1 1 1
0dB -10dB -20dB -30dB Speaker mute
For example an attenuation of 25dB on a selected output is given by: X X X1 0 1 0 0
Table 11.
MSB D7 D6
Bass/Treble
LSB Function D5 D4 D3 D2 D1 D0 Treble step 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 1 1 0 -14dB -12dB -10dB -8dB -6dB -4dB -2dB 0dB 0dB 2dB
15/20
Software specification Table 11.
MSB D7 D6 D5 D4 D3 1 1 1 1 1 1 D2 1 1 0 0 0 0 D1 0 0 1 1 0 0
TDA7348 Bass/Treble (continued)
LSB Function D0 1 0 1 0 1 0 4dB 6dB 8dB 10dB 12dB 14dB BASS STEPS
0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0
0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0
1 1 0 0 1 1 1 1 0 0 1 1 0 0 0 0
0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0
-10dB -8dB -6dB -4dB -2dB -0dB -0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB 146B 18dB
For example 12dB Treble and -8dB Bass give the following DATA BYTE: 0 0 1 1 1 0 0 1
16/20
TDA7348 Table 12.
MSB D7 D6 D5 D4 D3 D2 D1
Software specification Volume
LSB Function D0 0.31dB Fine attenuation steps 0 0 1 1 0 1 0 1 0dB -0.31dB -0.62dB -0.94dB 1.25dB Coarse attenuation steps 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0dB -1.25dB -2.5dB -3.75dB -5dB -6.25dB -7.5dB -8.75dB 10dB Gain / attenuation steps 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 20dB 10dB 0dB -10dB -20dB -30dB -40dB -50dB
For example to select -47.81dB volume the data byte is: 1 1 0 1 1 0 0 1 Power on RESET: All bytes set to 1 1 1 1 1 1 1 0
17/20
Package information
TDA7348
5
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 6.
DIM. MIN. A a1 b b1 C c1 D E e e3 F L S 7.4 0.4 17.7 10 1.27 16.51 7.6 1.27 0.291 0.016 0.1 0.35 0.23 0.5 45 (typ.) 18.1 10.65 0.697 0.394 0.050 0.65 0.299 0.050 0.713 0.419
SO-28 mechanical, data and package dimensions
mm TYP. MAX. 2.65 0.3 0.49 0.32 0.004 0.014 0.009 0.020 MIN. inch TYP. MAX. 0.104 0.012 0.019 0.013
OUTLINE AND MECHANICAL DATA
SO-28
8 (max.)
18/20
TDA7348
Revision history
6
Revision history
Table 13.
Date 14-Jan-2004 21-Jun-2004 26-Jan-2007
Document revision history
Revision 1 2 3 Initial release. Technical migration from ST-PRESS to EDOCS DMS DIP28 package removed, block diagram changed, layout modified. Changes
19/20
TDA7348
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